An Efficient Implementation of Advanced- Encryption-Standard Based on a Coarse-Grained Reconfigurable Processor

This paper presents a new approach to implement the Advanced Encryption Standard (AES), in the course, a Coarse-Grained Reconfigurable Processor, also called Reconfigurable CryptoProcessor is used to accomplish this assignment. The processor has been proved to be a candidate for cryptographic application. The prominent advantage of this processor is its high performance on cipher calculation tasks and flexibility in the switching of different algorithms. The method that we propose in this paper can achieve 10.47 Gbps in the 128-bits AES encryption at 300 MHz and just needs 5.01M Gates with high performance but of much more flexibility when compared with Field Programmable Gate Array (FPGA).